1. Field of the Invention
The present invention refers to a method of manufacturing a cylindrical storage node in a semiconductor device with a minimum loss difference of a conductive layer between the center and the edge of cell areas during an etch-back process of storage node isolation. The method of manufacturing a cylindrical storage node according to the present invention maintains electric capacitance uniformity over the entire cell area of a wafer and results in improved device reliability.
2. Description of the Related Art
A semiconductor memory device like a dynamic random access memory (DRAM) includes cell capacitors for storing data. As the degree of integration in a semiconductor memory device increases, the area of a cell unit decreases. Therefore, several approaches to guarantee availability of required capacitances in a limited space of a semiconductor memory device are researched and developed.
In general, cylindrical stack structures are known as universal capacitor structures. Referring to FIG. 1, in order to produce a cylindrical storage node in a semiconductor device, a poly plug 12 for bit line BC contacts is produced in an interlayer insulator 10, and a nitride layer is deposited as an etch stopping layer 14. As a next process step to produce the cylindrical storage node, a molding oxide layer 16 is deposited on the nitride layer 14, and a hole 18 is produced in the molding oxide layer 16 using a photolithographic etch process. The nitride layer 14, exposed in the bottom of the hole 18, is removed in an etch-back process and the poly plug 12 is exposed. Finally, a storage conductive layer 20 is deposited to a uniform thickness.
Referring to FIG. 2, a plugging material 22 is deposited to fill-up the inside of the hole 18 on the storage conductive layer 20. The plugging material 22 protects the bottom of the hole 18 in the storage node from being etched completely in the etch-back process of isolating the storage node. The height of the deposited plugging material 22 in the center area of the cell having the holes 18 is lower than the height of the deposited plugging material 22 in the cell surrounding areas without the holes 18 in an amount of 2500 to 3000 xc3x85.
In general, the time required to complete any etch-back process can be calculated by determining the average etch rate of the process and calculating the time necessary to etch through the layer. Etching is then allowed to continue for an over-etch period necessary to compensate any etch rate non-uniformity, layer thickness non-uniformity, or underlying topography. It is generally desirable to minimize the over-etch time so that the erosion of the underlying layer is minimized. A method of determining the nominal etching endpoint of the process allows such a reduction in over-etch time.
The endpoint of the etch-back process as illustrated in FIG. 3 is an etching time required for completely removing the storage conductive layer in cell surrounding areas. The etch-back process removes the plugging material 22 and the storage conductive layer 20 up to the location indicated by a broken line 30 in FIG. 3. Isolation for the storage node is then achieved among each of the holes 18. The center area of the cell is then etched more than the cell surrounding areas by an amount of about 3000 xc3x85so that the height of the cylindrical node becomes lower than before, which renders maintaining sufficient capacitances in the semiconductor memory device difficult.
Referring to FIG. 4, the etch-back process removes the plugging material 22 and the molding oxide layer 16 by employing an etch selectivity ratio between the oxide layer and the polysilicon and produces a cylindrical storage node 26.
One storage node isolation method is a lift-off method that removes the plugged oxide layer remaining inside of the hole 18 by employing an etchant solution consisting of hydrogen fluoride (HF). The HF etchant etches not only the plugged oxide layer but it also etches the interlayer insulator 10 underlying the etch stopping layer 14, in the edge areas of a wafer. As a result, defects such as bridge defects are generated as the next process steps are performed on the wafer. Such defects may lead to failure in driving the semiconductor device, such as twin-bit failure in electrical die sorting EDS tests, which decreases the reliability of the final semiconductor devices.
Another method of storage node isolation employs a flowable oxide as the plugging material inside of the hole 18 and isolates the storage node by a chemical-mechanical polishing (CMP) process. However, the CMP process changes the surface morphology of a wafer and produces non-uniform heights of the storage nodes between cells or chips because of micro scratches, which also result in lowering device reliability.
To overcome the above described problems, the present invention provides a method of manufacturing a cylindrical storage node of a semiconductor device that minimizes a loss difference of the conductive layer, between the center and the edge areas of a cell, caused by an etch-back process of storage node isolation. The method of manufacturing a cylindrical storage node of a semiconductor device according to the present invention maintains uniform electrical capacitances over the entire cell areas of a wafer, which results in improved reliability of the semiconductor device.
In accordance with a preferred embodiment of the present invention, there is provided a method of manufacturing a cylindrical storage node in a semiconductor device, comprising forming a plurality of holes in a molding insulator on cell areas, etching an etch stopping layer at the bottom of each hole and exposing a poly plug, depositing a conductive layer of a uniform thickness on the molding insulator having the plurality of holes, filling a plugging material on the conductive layer deposited on the plurality of holes, removing an upper portion of the plugging material by an etchback process to expose an upper portion of the molding insulator and the conductive layer in surrounding areas of each hole, removing the conductive layer exposed in surrounding areas of each hole to isolate the conductive layer in each hole from the conductive layer in other holes, removing the plugging material from each hole, and removing the remaining molding insulator.
In another embodiment of the present invention, there is provided another method of manufacturing a cylindrical storage node in a semiconductor device, comprising forming a plurality of holes in a molding insulator on cell areas, etching an etch stopping layer at the bottom of each hole and exposing a poly plug, depositing a conductive layer of a uniform thickness on the molding insulator having the plurality of holes, filling a plugging material, which is an oxide layer, on the conductive layer deposited on the plurality of holes, removing an upper portion of the plugging material by a wet etch process to expose an upper portion of the molding insulator and the conductive layer in surrounding areas of each hole, removing the conductive layer exposed in surrounding areas of each hole to isolate the conductive layer in each hole from the conductive layer in other holes, removing the plugging material from each hole, and removing the remaining molding insulator.
According to a feature of the present invention, the plugging material is a photoresist which can be etched during the etch-back process by a mixed gas of oxygen and nitrogen as a reactive gas. According to another feature of the present invention, the plugging material is an oxide layer, which is one of undoped silicate glass (USG), a boron-phosphorus-silicate glass (BPSG), a silicate on glass (SOG), and a flowable oxide. According to another feature of the present invention, the oxide layer can be etched during the etch-back process by reactive gas mixtures such as CHF3/CO/Ar or C5F8/O2/Ar to utilize Cxe2x80x94C, CFx radicals that etch the oxide layer selectively, or by a wet etch process involving a solution containing HF.
According to a feature of the present invention, the etchant used for removing the exposed conductive layer is a main gas SF6 and an additional gas Cl2 or O2that performs an isotropic etch to the exposed conductive layer. According to another feature of an embodiment of the present invention, the plugging material remaining inside of the multiple holes is removed by an ashing process or a wet etch process.
These and other features of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows.